Not applicable.
Not applicable.
1. Field of the Invention
The present invention relates to testing of integrated circuits, and more particularly to a method for performing built-in self repair operations without the need to perform built-in self test.
2. Description of the Related Art
Improvements in semiconductor processes are making possible integrated circuits of increasing size and complexity. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems, including memories, can now be reduced to a single integrated circuit or application specific integrated circuit (ASIC) device. These integrated circuits (also referred to as xe2x80x9cdiexe2x80x9d or xe2x80x9cchipsxe2x80x9d) may use many functions that previously could not be implemented on a single die. It is a common practice for the manufacturers of such integrated circuits to thoroughly test device functionality at the manufacturing site. However, due to the complex nature of today""s integrated circuits and a concomitant sensitivity to variations in manufacturing processes, manufacturers are constantly confronted with new testing challenges.
Before manufacturers release integrated circuits for shipment, the devices typically undergo a variety of testing procedures. In ASIC devices incorporating integrated memories, for example, specific tests are performed to verify that each of the memory cells within the integrated memory array(s) is functioning properly. This testing is necessary because perfect yields are difficult to achieve. It is not uncommon for a certain percentage of unpackaged ASIC die to contain memory cells which fail testing processes, due largely to non-systemic manufacturing defects. Such manufacturing issues are likely to increase as process geometries continue to shrink and the density of memory cells increases. Even today, up to 100 Mbits or more of dynamic random access memory (DRAM), or several megabits of static random access memory (SRAM) or flash memory can be integrated onto a single integrated circuit.
A number of ASIC memory testing strategies have evolved, many of which involve use of an external memory tester or Automated Test Equipment (ATE). If memory is accessible from input/output (I/O) pins, either directly or by multiplexing, a hardware test mode can be utilized. In this mode, a production test system accesses the memory directly by writing to and reading from the memory bits. While this methodology does not use any chip area other than simple multiplexing circuitry, it is limited to on-chip memories and other circuitry accessible via I/O pins. Another drawback of this approach is that ATE capabilities are generally not available to end-users once the devices have been shipped, making it difficult to detect faults occurring after shipment.
If an embedded memory is buried deeply within an ASIC, built-in self-test (BIST) is often considered the most practical and efficient test methodology and is becoming increasing popular with semiconductor vendors. BIST allows timely testing of the memory with a reasonably high degree of fault coverage, without requiring complex external test equipment and large amounts of external access circuitry. With BIST, memory or logic circuitry can be tested at any time in the field. This capability offers some degree of continued fault protection.
BIST refers in general to any test technique in which test vectors are generated internal to an integrated circuit or ASIC. Test vectors are sequences of signals that are applied to integrated circuitry to determine if the integrated circuitry is performing as designed. BIST can be used to test memories located anywhere on the ASIC without requiring dedicated I/O pins, and can be used to test memory or logic circuitry every time power is applied to the ASIC, thereby allowing an ASIC to be easily tested after it has been incorporated in an end product. A number of software tools exist for automatically generating BIST circuitry, including RAMBIST Builder by LSI Logic of Milpitas, Calif. Such software produces area-efficient BIST circuitry for testing memories, and reduces time-to-market and test development costs.
In the BIST approach, a test pattern generator and test response analyzer are incorporated directly into the device to be tested. BIST operation is controlled by supplying an external clock and via use of a simple commencement protocol. BIST test results are typically compressedxe2x80x94usually to the level of xe2x80x9cpassedxe2x80x9d or xe2x80x9cfailedxe2x80x9d. At the end of a typical structured BIST test, or xe2x80x9crunxe2x80x9d, a simple pass/fail signal is asserted, indicating whether the device passed or failed the test. Intermediate pass/fail signals may also be provided, allowing individual memory locations or group of locations to be analyzed. Unlike external testing approaches, at-speed testing with BIST is readily achieved. BIST also alleviates the need for long and convoluted test vectors and may function as a surrogate for functional testing or scan testing. Since the BIST structures exist and remain active throughout the life of the device, BIST can be employed at the board or system level to yield reduced system testing costs, and to reduce field diagnosis and repair costs.
In addition to the aforementioned testing procedures, manufacturers use a number of techniques to repair faulty memories when feasible. Such techniques include bypassing defective cells using laser procedures and fused links that cause address redirection. However, such techniques are limited to one-time repair and require significant capital investment. Further, these techniques may leave integrated circuits useless if the repaired memories become defective after shipment from the manufacturing sitexe2x80x94even where test equipment is available to end users, traditional field repairs have been expensive, time consuming, and largely impracticable.
In order to enhance the repair process, on-chip built-in self repair (BISR) circuitry for repairing faulty memory cells has evolved. BISR circuitry functions internal to the integrated circuit without detailed interaction with external test or repair equipment. In the typical BISR approach, suitable test algorithms developed and implemented in BIST or BIST-like circuitry. These test patterns may be capable of detecting stuck-at, stuck-open, bridging faults and retention faults during memory tests. Following execution of the test patterns, the BISR circuitry analyzes the BIST xe2x80x9csignaturexe2x80x9d (results) and, in the event of detected faults, automatically reconfigures the defective memory utilizing redundant memory elements to replace the defective ones. A memory incorporating BISR is therefore defect-tolerant. The assignee of the present invention, LSI Logic Corporation, has addressed different methods of repairing faulty memory locations utilizing BIST and BISR circuitry, as disclosed in U.S. Pat. No. 5,764,878, entitled xe2x80x9cBUILT-IN SELF REPAIR SYSTEM FOR EMBEDDED MEMORIESxe2x80x9d, U.S. patent application No. 09/209,938, entitled xe2x80x9cREDUNDANCY ANALYSIS FOR EMBEDDED MEMORIES WITH BUILT-IN SELF TEST AND BUILT-IN SELF REPAIRxe2x80x9d filed Dec. 11, 1998, now U.S. Pat. No. 6,067262, and U.S. patent application No. 09/209,996, entitled xe2x80x9cTESTING SCHEME FOR EMBEDDED MEMORIES USING BISR AND FUSE IDxe2x80x9d filed Dec. 11, 1998, now U.S. Pat. No. 6,367,042, all of which are hereby incorporated by reference as if set forth in their entirety.
BISR compliments BIST because it takes advantage of on-chip processing capabilities to re-route bad memory bits rather than using an expensive and slow laser burning process to replace faulty memory locations. Some BISR circuitry is capable of repairing the faulty memory locations by redirecting the original address locations of faulty memory lines to the mapped addressed locations of the redundant columns and rows. Options for repair include either row and column replacement when a bad bit is found in a particular row or column.
An important feature of any integrated circuit is its reliability. Engineers strive to design integrated circuits that operate under a range of conditions (including temperatures and voltages) without malfunctioning. Therefore, it is often desirable to test dies (or xe2x80x9cdicexe2x80x9d) under realistic field conditions during the manufacturing production cycle to ensure operability. This testing is done before singulation (i.e., separation) of the individual dies from a wafer. Furthermore, instead of using costly external test patterns to test memory locations, it is desirable to use the BIST circuitry with external ATE. The external tester is programmed to xe2x80x9ctestxe2x80x9d a die""s embedded memory by examining the outputs of the its BIST circuitry. With stand alone memory devices, manufacturers use expensive memory ATEs/redundancy analyzers to test over a range of conditions. Typically, a worst set of operating conditions is applied and any detected faults are repaired, if possible, using fuse structures that are integrated within the memory array of the stand-alone memory device.
With embedded memories, current BIST methodologies may not adequately detect memory locations having faults that are dependent on operating conditions (e.g., normal variations in voltage, timing, power supply disturbances and temperature). Even with BIST/BISR, memory elements can pass the power-up BIST under an initial set of operating conditions, only to fail during normal operation when the die is subsequently subjected to another set of operating conditions. Further, since BISR structures have a limited number of redundant memory locations, a device may be repairable only under select operating conditions. The problem may be exacerbated by the rigors of the packaging process, which may give rise to failure mechanisms not present in a given integrated circuit before singulation. Since BIST/BISR is typically run only once during a power cycle, any memory locations that fail after power-up may not be repaired. Such failures may cause the chip to be unsuitable for its intended use. Additionally, the execution time and off-chip circuitry required by BIST circuitry may be undesirable for certain end products.
Briefly, the present invention provides a method and circuitry for providing memory fault information to and performing built-in self repair operations in an integrated circuit without the requirement of first performing a built-in self test procedure. In accordance with the invention, a fuse array or other non-volatile memory device is provided to store information related to defective memory locations identified during the manufacturing process.
In the disclosed embodiment of the invention, an integrated circuit die of a semiconductor wafer is provided with BIST/BISR circuitry and an embedded memory or similar circuit. The integrated circuit also includes a fuse array or other none-volatile circuitry capable of storing address information for defective memory locations. During manufacture, the integrity of the embedded memory of each integrated circuit die is preferably tested under a variety of conditions (also referred to as stress factors) via the BIST/BISR circuitry. The results of these tests are stored and compiled in ATE. The results are also referred to as BIST signatures or memory repair solutions. If the repair solutions indicate that the embedded memory is repairable, the on-chip fuse array of the integrated circuit is programmed with information indicative of all of the detected defective memory locations. Programming of the fuse array may occur prior to or following singulation and packaging of the integrated circuit die.
Once packaged and incorporated within an end product, the built-in self repair circuitry of the integrated circuit die is not executed upon power up. Instead, the repair information stored in the fuse array is provided to address remap circuitry within the BISR circuit. The repair information represents faulty memory locations detected during the manufacturing testing process under a variety of operating conditions. When an access to one of these memory locations is attempted during normal operation of the integrated circuit, the BISR circuitry remaps the memory operation to a redundant memory element.
Thus, an integrated circuit implemented according to the present invention obviates the requirement of executing built-in self test each time power is supplied to the circuit, thereby simplifying the board-level design of the end product. Programming of the fuse array can be accomplished with any logic tester, and does not require redundancy analyzers or other expensive memory tester hardware. Further, because the stored fault information reflects test data gathered at a variety of operating conditions, the built-in self repair circuitry is capable of providing a higher degree of fault coverage than traditional BIST methods.